Recently, in semiconductor integrated circuits such as high-speed CMOS circuits, the operating frequency of the circuits has become higher and hence the length of one clock cycle has been reduced. Further, as integration density and function level of a semiconductor integrated circuit become higher, clock interconnections become longer. In a semiconductor integrated circuit with clock synchronous circuits, such as latches or registers, which also perform sampling of data in response to a clock transition, a clock tree system is employed. This technique allows for matching delays from a clock source, such as a clock input pin or an internal clock generation circuit, to the respective clock synchronous circuits, and thereby performing clock distribution. In the clock tree system, as shown in FIG. 12, clock buffer circuits (also referred to as “CTS (Clock Tree Synthesis) buffer circuits) INV101 to INV117 are disposed along clock propagation paths. A conventional clock buffer circuit is comprised of a PMOS transistor and an NMOS transistor. In case wherein the clock buffer circuit is composed of a CMOS inverter, an input signal is supplied to commonly coupled gates of a PMOS transistor and an NMOS transistor connected in series between a high-potential power supply and a low-potential power supply, and an output signal of the clock buffer circuit is outputted from a connection point between a drain of the PMOS transistor and the drain of the NMOS transistor. For speeding up a high-level output driven by the PMOS transistor which is turned on, a size of the PMOS transistor is made large, while the size of the NMOS transistor is made small and hence a βp/βn ratio is made large, thereby achieving speeding up the high-level output, where the βp/βn ratio is a ratio of gain coefficients between the PMOS transistor and the NMOS transistor that constitute the CMOS inverter. The β is given by (μ∈/tox)(W/L), where μ represents a carrier mobility, ∈ represents a dielectric constant of a gate dielectric film, tox represents a thickness of the gate dielectric film, W represents a channel width, and L represents a channel length. However, when achieving the speeding up by increasing the βp/βn ratio, the size of the NMOS transistor must be made especially smaller because of a cell size constraint or the like, so that a fall time of an output waveform to a low level becomes slow. Further, if the βp/βn ratio is increased by reducing the size of the NMOS transistor, sensitivity to manufacturing variations is increased, as a result of which, an operation margin will be also extremely deteriorated.
In Japanese Patent Kokai Publication JP-A-8-321768, a buffer circuit is disclosed that enabled a high-speed operation. In this buffer circuit, a charging circuit composed of a pMIS transistor and a discharging circuit composed of an nMIS transistor are connected in series. An output of a rising-edge detection circuit for detecting a rising edge of an input signal is supplied to a gate of the pMIS transistor, while the output of a falling-edge circuit for detecting a falling edge of the input signal is supplied to the gate of the nMIS transistor. The output of a non-inverting gate for receiving the input signal is connected to the connection node between the pMIS transistor and the nMIS transistor. While one of the pMIS transistor and the nMIS transistor is turned on, the other is turned off, so that a short-circuit current does not flow through the nMIS and pMIS transistors, thereby enabling the high-speed operation. In the buffer circuit in the above-mentioned publication, the edge detection circuits are inserted between an input terminal and the gate of the pMIS transistor and between the input terminal and the gate of the nMIS transistor. Both rise and fall transitions of an output signal are delayed by times corresponding to respective propagation delays of the edge detection circuits and hence the circuit is unsuitable as a high-speed buffer circuit. In other words, in the buffer circuit described in the above-mentioned publication, in case wherein a clock synchronous circuit such as a latch or a register samples data by using only one of a rising edge and a falling edge of a clock signal, the clock signal edge used is delayed as with the clock signal edge not used.